Takuya Kojima

Profile page

Logo

Amano-Laboratory, Depertment of Information and Computer Science, Keio University

E-mail:

ORCID iD iconorcid.org/0000-0002-5943-444X

Hosted on GitHub Pages — Theme by orderedlist

Profile

English Ver. (-> Japanese Ver.)

Research Interests


Biography

Education

Research Experience

Work Experience

Qualifications


Scholarships

  1. Repayment Exemption for Graduate Students with Excellent Achievements JASSO type-1 scholarship exemption of all of loan (2019)

Grants

Awards

  1. IEEE CEDA AJJC Design Gaia Best Poster Award (2019)
  2. IEICE CPSY Young Presentation Award (2018)

For co-authors

  1. IEICE CPSY Young Presentation Award (2020)

Publications (selected)

The full list is here.

International Journals

  1. Takeharu Ikezoe, Takuya Kojima, Hideharu Amano, “Recovering faulty Non-volatile Flip Flops for Coarse-Grained Reconfigurable Architectures”, IEICE Transactions on Electronics, Vol.E104-C, No.6, pp.215-225, Jun. 2021. DOI: 10.1587/transele.2020LHP0002.

  2. Takuya Kojima, Nguyen Anh Vu Doan, Hideharu Amano, “GenMap: A Genetic Algorithmic Approach for Optimizing Spatial Mapping of Coarse Grained Reconfigurable Architectures”, IEEE Transactions on Very Large Scale Integration Systems (VLSI), Vol. 28, no. 11, pp.2383-2396, Nov 2020. DOI: 10.1109/TVLSI.2020.3009225. [IEEE Xplore]

  3. Takuya Kojima, and Hideharu Amano, “A Fine-Grained Multicasting of Configuration data for Coarse-Grained Reconfigurable Architectures”, IEICE Transactions on Information and Systems, Vol.E102-D,No.7,pp.1247-1256,Jul. 2019. DOI:10.1587/transinf.2018EDP7336. [Paper]

  4. Takuya Kojima, Naoki Ando, Hayate Okuhara, Ng. Anh Vu Doan and Hideharu Amano, “Optimization of Body Biasing for Variable Pipelined Coarse-Grained Reconfigurable Architectures”, IEICE Transactions on Information and Systems, Vol.E101-D, No.6, pp.1532-1540, Jun 2018. DOI: 10.1587/transinf.2017EDP7308. [Paper]

International Conferences (Peer-reviewed)

  1. Takeharu Ikezoe, Takuya Kojima, and Hideharu Amano, “A Coarse-Grained Reconfigurable Architecture with a Fault Tolerant Non-volatile Configurable Memory”, 2019 International Conference on Field-Programmable Technology (FPT),Tianjin, China, December, 2019.

  2. Takuya Kojima, Naoki Ando, Yusuke Matsushita and Hideharu Amano, “Demonstration of Low Power Stream Processing Using a Variable Pipelined CGRA”, 29th International Conference on Field Programmable Logic and Applications (FPL), Barcelona, Spain, September, 2019. (Demo Paper) [Paper] [Poster]

  3. Takuya Kojima and Hideharu Amano, “A Configuration Data Multicasting Method for Coarse-Grained Reconfigurable Architectures”, 28th International Conference on Field Programmable Logic and Applications (FPL), Dublin, Ireland, August, 2018. [Paper] [Poster]

  4. Takuya Kojima, Naoki Ando, Yusuke Matsushita, Hayate Okuhara, Nguyen Anh Vu Doan and Hideharu Amano, “Real Chip Evaluation of a Low Power CGRA with Optimized Application Mapping”, International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2018), Canada, June, 2018. [Paper] [Slide]

  5. Takuya Kojima, Naoki Ando, Hayate Okuhara, Hideharu Amano, “Glitch-aware Variable Pipeline Optimization for CGRAs”, ReConFig 2017, Mexico, December 2017. [Paper] [Poster]

  6. Takuya Kojima, Naoki Ando, Hayate Okuhara, Ng. Anh Vu Doan, Hideharu Amano, “Body Bias Optimization for Variable Pipelined CGRA”, 27th International Conference on Field-Programmable Logic and Applications(FPL), Belgium, September 2017. [Paper] [Poster]

Japanese domestic conferences/Technical reports

  1. Ayaka Ohwada, Takuya Kojima, Hideharu Amano, “Construction and Evaluation of Software Development Environment for CGRA using LLVM “, ETNET 2020, Yoron-cho Chuou-Kouminkan, Kagoshima, Feb. 2020. (Young Presentation Award)

  2. 小島拓也, 天野英晴, “CGRAのためのアプリケーションマッピングフレームワークGenMapの実装と実機評価”, デザインガイア2019 -VLSI設計の新しい大地-, 愛媛県男女共同参画センター, 愛媛, 2019年11月. [Paper] (IEEE CEDA AJJC Design Gaia Best Poster Award)

  3. Takuya Kojima, Naoki Ando, Yusuke Matsushita, Hayate Okuhara, Ng. Doan Anh Vu, Hideharu Amano, “Low Power Stream Processing on a Variable Pipelined Accelerator CCSOTB2”, Hida Area Local Industry Promotion Center, Takayama-shi, Nov. 2018. [Paper] (Young Presentation Award)

Acknowledgement

A part of our work is supported by a Grant-in-Aid for Scientific Research(S) Grant Number 25220002, a Grant-in-Aid for Scientific Research(B) Grant Number 18H03215, a Grant-in-Aid for JSPS Fellows Grant Number 19J21493 and JST CREST Grant Number JPMJCR19K1. Also, A part of our work is supported by VLSI Design and Education Center(VDEC), the University of Tokyo in collaboration with Synopsys, Inc. and Cadence Design Systems, Inc.